How to design a code converter using VHDL

Code converter finds application in digital system design and in this blog it is shown how to design a code converter using VHDL. There are many instances that requires code conversion for example in communication system encoding. For example binary to excess 3 code or binary to gray code or gray code to excess 3 code.

The conversion of codes from one to another can be done in different ways. One way is to construct state diagram. Another way is simply to use case statements or if-then-elsif or select statements. There may be also other ways.

Here it is shown how case statement and select statement can be using to convert binary code to excess 3 code.

The first thing to know is what and how they need to converted. 4bit excess 3 code is obtained by adding 0011 to the 4 bit binary value.

It is helpful to construct a truth table for the conversion.

There are 16 codes listed above, but here only 8 codes will be illustrated as this is enough to illustrate how to implement the conversion.

Let x and y be the input and output respectively, that is x is the binary 4 bit input and y is the 4 bit excess 3 code output.

So the entity declaration would look this,

entity code_converter is
    port(
    x : in std_logic_vector(3 downto 0);
    y : out std_logic_vector(3 downto 0)
    )
end code_converter;

Now to the question of How to design a code converter using VHDL?

First it is shown how select statement can be used to do the code conversion. The architecture for the code converter using the select statment is as follows,

architecture Select_RTL of code_converter is

begin
        with x select
        y <= "0011" when "0000",
        "0100" when "0001",
        "0101" when "0010",
        "0110" when "0011",
        "0111" when "0100",
        "1000" when "0101",
        "1001" when "0110",
        "1010"    when "0111",
        "XXXX" when others;
               
end Select_RTL;

Now the same code conversion can be achieved using case statement as follows,

architecture Case_RTL of code_converter is

begin
    process (x)
    begin
        case x is
            when "0000" => y <= "0011";
            when "0001"    => y <= "0100";
            when "0010"    => y <= "0101";
            when "0011" => y <= "0110";
            when "0100" => y <= "0111";
            when "0101" => y <= "1000";
            when "0110" => y <= "1001";
            when "0111" => y <= "1010";
            when others => y <= "XXXX";
        end case;
       
    end process;
end Case_RTL;

Yet there is another method that can be used to implement this conversion. It is much simpler than the above two methods.

architecture add_RTL of code_converter is

signal y_int : integer;

begin
    y_int <= to_integer(unsigned(x)) + 3;
    y <= std_logic_vector(to_unsigned(y_int,4));

end add_RTL;

In this method, the input binary x was converted to integer and 3 was added to it. The result was converted back to binary bits.

See the tutorial- http://appliedelectronicsengineering.blogspot.com/2014/10/how-to-convert-stdlogicvector-to.html to see how to convert between different data types.

So in this way we can use different methods to design a code converted using VHDL.

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