Flash ADC priority encoder vhdl design

The priority encoder is useful in many application not only in digital circuit but also in the mixed circuit such as analog to digital converter(ADC). For example Flash type ADC uses priority encoder to select which of the different inputs should be sampled and encoded into digital digital bits. The following shows how Flash type ADC works first then VHDL model for the priority encoder is developed.

There are different types of ADC and one of them is Parallel Comparator ADC or Flash ADC. The Flash ADC converts analog signal to digital signal very fast compared to other types of ADC such as Dual Slope ADC or Successive Approximation Register(SAR) ADC. That is its conversion time is small. The disadvantage of Flash ADC is that if the resolution is to be increased then the number of comparator has to be increased which makes the converter bulky.

The Flash ADC can be described as being composed of 3 different constituents- the Voltage Divider Resistor(VDR) network, the Comparators(op-amp) and the priority encoder.

The VDR network is used to create voltage reference with which the input analog signal is compared using the comparator. The voltage reference points is created using same value resistor and the number of the reference points to be created is decided by the number of digital bits one wants to produce. As an example, if n=3 bits is used for the digital signal output then the number of the voltage reference point is 2^3-1= 7. Next the input analog signal which is to be converted into digital signal is done by fedding the analog signal to the inputs of the comparators. The analog signal is fed into the non-inverting terminal of the op-amp and the voltage references are connected to the inverting terminal of the op-amp. The output of those op-amp becomes high in which the input signal voltage is greater than the reference voltage. If there are 7 op-amps comparator, then the analog signal voltage becomes greater than the reference voltage starting from the 3rd op-amp then the rest of the op-amp output also becomes high. That is the 3rd, 4th, 5th, 6th and 7th op-amp output are high.

The priority encoder gives priority to that op-amp output which is first activated high, in this case the 3rd op-amp. Then the priority encoder outputs digital bits corresponding to the digit 5.

Thus one use of priority encoder is in the ADC converter. Now the following describes how a priority encoder is modelled in VHDL.



The input to the priority encoder for the 3 bits digital signal output from the ADC are the 7 outputs from the comparator(op-amps). Depending upon which output gets activated first we produce corresponding digital outputs.

Let Cinp be the input to the priority encoder and Dcode be the digital codes. Then the entity declaration of this priority encoder becomes-

entity priority_encoder is
    port(
    Cinp : in std_logic_vector(7 downto 0);
    Dcode : out std_logic_vector(2 downto 0)
    );
end priority_encoder;

Next we need to create the architecture for the priority encoder. The following is the VHDL code for the flash type ADC priority encoder:

architecture priority_encoder_arch of priority_encoder is
begin
Dcode <= "111" when (Cinp(7)=1) else
"110" when (Cinp(6)=1) else
"101" when (Cinp(5)=1) else
"100" when (Cinp(4)=1) else
"011" when (Cinp(3)=1) else
"010" when (Cinp(2)=1) else
"001" when (Cinp(1)=1) else
"000"; 
end priority_encoder_arch;

Related Posts by Categories