1101 sequence detector state diagram with VHDL code

A sequence detector is good example of sequential logic circuit also called FSM(Finite State Machine). A 1101 sequence detector detects 1101 consecutive bits in a string of binary bits. It is good practice to draw the state diagram of the sequence of process that happens to capture understanding of the behavior of the circuit. In the design of 1101 sequence detector, the design of state diagram is the first step, which then is followed by the creation of state table, state transition table and finally the circuit itself and testing being the final step.

Readers are recommended to read the following posts which are related to this blog post. A detailed steps to construct a sequential circuit is provided in the blog post- How to design Sequence Detector in 10 easy steps. Also another post useful in sequential circuit is- how to design Moore sequential circuit in Simulink. And futhermore this post- how to use Xilinx Schematic editor with example of sequence detector shows how xilinx software can be used to design and verify the sequence detector.

The state diagram of 1101 sequence detector is shown below-

State S1:

 Beginning at state S1 when 0 is received it stays in the same state because it has nothing to remember and the output is 0 because the sequence 1101 is not detected. Only at the instant when 1101 sequence is detected the output is high, that is, 1. Also remember that the flip flops should be used when things are to be remembered by the circuit. When 1 arrives when in state S1, then it goes to next state S2 and it remembers that 1 was received which is part of the sequence 1101 which is to be detected.

State S2:
When in state S2, when 1 arrives, since it is part of the sequence it goes to next state S3, meaning it remembers 1. When 0 is received it cannot go to next state S3(since 1 received has occupied the transition condition and because 0 is not part of the sequence and there is nothing to remember), and it cannot remain in the same state S2 because this would mean 010 indefinite loop while in state S2, therefore it goes back to the initial state S1. Consider 100 is received and machine remains in S2 when 0 is received, then because of 1 the state changes from S1 to S2, then 0 is received then the machine stays in S2 and when another 0 is received then it stays again in S2. But consider when 100 is received and machine goes back to S1, then when 1 is received it changes state from S1 to S2, when 0 is received then goes back to S1 and when another 0 is received it stays in S1.

State S3:
When in state S3, when 0 is received then since it is part of the sequence 1101 it goes to new state S4 because the machine has to remember the new bit 0 as part of the sequence detection algorithm. When 1 is received it stays in the same state.

State S4:
When in state S4, when 1 is received then since it is part of the sequence 1101 to be detected it goes to S2. And when 0 is received then it goes back to initial state S1. At this point the machine outputs 1.

Following is a simulated digital waveform for the seqence 10101101010110001

The graph shows that the output z is high when 1101 is detected in the sequence x = 10101101010110001

The VHDL code for implementing this sequence detector is below-

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity sequence_detector is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
x: in STD_LOGIC;
z: out STD_LOGIC);
end sequence_detector;

architecture sequence_detector_arch of sequence_detector is

type seq_detect_type is (
    S1, S2, S3, S4
);

signal seq_detect: seq_detect_type;

begin

seq_detect_machine: process (clk)
begin
if clkevent and clk = 1 then
if rst=1 then
seq_detect <= S1;

else

case seq_detect is
when S1 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;
when S2 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S1;
end if;
when S3 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S4;
end if;
when S4 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;

when others =>
null;

end case;
end if;
end if;
end process;

z_assignment:
z <= 0 when (seq_detect = S1 and x = 1) else
     0 when (seq_detect = S1 and (x = 0 and not (x = 1))) else
     0 when (seq_detect = S2 and x = 1) else
     0 when (seq_detect = S2 and (x = 0 and not (x = 1))) else
     0 when (seq_detect = S3 and x = 1) else
     0 when (seq_detect = S3 and (x = 0 and not (x = 1))) else
     1 when (seq_detect = S4 and x = 1) else
     0 when (seq_detect = S4 and (x = 0 and not (x = 1))) else
     0;

end sequence_detector_arch;

The testbench code for the sequence detector is,

library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sequence_detector_tb is
end sequence_detector_tb;

architecture TB_ARCHITECTURE of sequence_detector_tb is

component sequence_detector
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end component;

signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal x : STD_LOGIC;
signal z : STD_LOGIC;

begin

UUT : sequence_detector
port map (
clk => clk,
rst => rst,
x => x,
z => z
);

clk_process : process
begin
clk <= 0;
wait for 5 ns;

clk <= 1;
wait for 5 ns;

end process;

sti_process: process
begin
x <= 0;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 1;
wait for 10 ns;

x <= 0;
wait for 10 ns;

end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_sequence_detector of sequence_detector_tb is
for TB_ARCHITECTURE
for UUT : sequence_detector
use entity work.sequence_detector(sequence_detector_arch);
end for;
end for;
end TESTBENCH_FOR_sequence_detector;

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