5.Samsung Galaxy Mega 6.3 I9200
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This is a beginner embedded system programming tutorial where it is shown how to write a C program that turns on a sound alarm when a switch is closed. The 80C51 microcontroller is used to do this. The switch is connected to the pin 0 of port 1 and the sound device is connected to the pin 0 of port 0. The C program continuously monitors the state of the switch and if the switch is switched On, then it sounds alarm that beeps 5 times with one second interval.
Following is the schematic diagram.
The C program is below:
#include <Reg51.H>
#define ON 0
#define OFF 1
sbit BUZZ = P0^0;
sbit BUTTON = P1^0;
void OneSec() // 1 sec delay function
{
unsigned int x;
for(x=0;x<33000;x++);
}
main() //main function
{
int i;
BUZZ = OFF;
while(1)
{
if(BUTTON==OFF)
{}
else
{
for(i=1;i<=5;i++)
{
BUZZ = ON;
OneSec();
BUZZ = OFF;
OneSec();
}
}
}
}
We defined ON and OFF as 0 and 1 using the preprocessor directive statements #define so that we can write ON and OFF keywords in the program code and it makes it easy to understand the code.
Then we defined two variables BUZZ and BUTTON as sbit data types and assigned them to the port 0, pin 0 and port 1, pin 0.
The OneSec() is a function which when executed takes 1 second. This function will be called in the main function to insert 1 second time interval between sound on and off.
The main function starts with variable initialization. The int i declares an integer i which will be required in outputting 5 signals to the sound device. Then BUZZ = OFF is used to make the port 0, pin 0 an output.
The while(1) statement is used to continuously execute the statements following it(read the state of switch and buzz sound). The if and else statements are used to sound the alarm if the switch is closed or not to sound if it is open.
In the above C program, we could have replaced while(1) with for(;;). Also we could have used while(BUTTON==OFF) instead of if(BUTTON==OFF) in which case the else(and the if) would not be required.
See another beginner embedded C programming tutorial- How to write C program to read/write ports of a microcontroller
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4.Samsung Galaxy Note 2 N7100
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Virtua Tennisâ„¢ Challenge apk Download
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Virtua Tennis™ Challenge apk
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Requires Android : 2.3 and up
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Size : 379M
Original Post From http://apkandroiddownloads.blogspot.com
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★ Multiplayer: Challenge your friend face to face over Bluetooth
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Check out other SEGA Games:
Super Monkey Ball™ 2: Sakura Edition
ChuChu Rocket!™
Sonic CD™
Sonic 4™: Episode II
FOLLOW US: twitter.com/sega
LIKE US: facebook.com/sega
VISIT US: http://blogs.sega.com/
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1101 sequence detector state diagram with VHDL code
A sequence detector is good example of sequential logic circuit also called FSM(Finite State Machine). A 1101 sequence detector detects 1101 consecutive bits in a string of binary bits. It is good practice to draw the state diagram of the sequence of process that happens to capture understanding of the behavior of the circuit. In the design of 1101 sequence detector, the design of state diagram is the first step, which then is followed by the creation of state table, state transition table and finally the circuit itself and testing being the final step.
Readers are recommended to read the following posts which are related to this blog post. A detailed steps to construct a sequential circuit is provided in the blog post- How to design Sequence Detector in 10 easy steps. Also another post useful in sequential circuit is- how to design Moore sequential circuit in Simulink. And futhermore this post- how to use Xilinx Schematic editor with example of sequence detector shows how xilinx software can be used to design and verify the sequence detector.
The state diagram of 1101 sequence detector is shown below-
State S1:
Beginning at state S1 when 0 is received it stays in the same state because it has nothing to remember and the output is 0 because the sequence 1101 is not detected. Only at the instant when 1101 sequence is detected the output is high, that is, 1. Also remember that the flip flops should be used when things are to be remembered by the circuit. When 1 arrives when in state S1, then it goes to next state S2 and it remembers that 1 was received which is part of the sequence 1101 which is to be detected.
State S2:
When in state S2, when 1 arrives, since it is part of the sequence it goes to next state S3, meaning it remembers 1. When 0 is received it cannot go to next state S3(since 1 received has occupied the transition condition and because 0 is not part of the sequence and there is nothing to remember), and it cannot remain in the same state S2 because this would mean 010 indefinite loop while in state S2, therefore it goes back to the initial state S1. Consider 100 is received and machine remains in S2 when 0 is received, then because of 1 the state changes from S1 to S2, then 0 is received then the machine stays in S2 and when another 0 is received then it stays again in S2. But consider when 100 is received and machine goes back to S1, then when 1 is received it changes state from S1 to S2, when 0 is received then goes back to S1 and when another 0 is received it stays in S1.
State S3:
When in state S3, when 0 is received then since it is part of the sequence 1101 it goes to new state S4 because the machine has to remember the new bit 0 as part of the sequence detection algorithm. When 1 is received it stays in the same state.
State S4:
When in state S4, when 1 is received then since it is part of the sequence 1101 to be detected it goes to S2. And when 0 is received then it goes back to initial state S1. At this point the machine outputs 1.
Following is a simulated digital waveform for the seqence 10101101010110001
The graph shows that the output z is high when 1101 is detected in the sequence x = 10101101010110001
The VHDL code for implementing this sequence detector is below-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity sequence_detector is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
x: in STD_LOGIC;
z: out STD_LOGIC);
end sequence_detector;
architecture sequence_detector_arch of sequence_detector is
type seq_detect_type is (
S1, S2, S3, S4
);
signal seq_detect: seq_detect_type;
begin
seq_detect_machine: process (clk)
begin
if clkevent and clk = 1 then
if rst=1 then
seq_detect <= S1;
else
case seq_detect is
when S1 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;
when S2 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S1;
end if;
when S3 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S4;
end if;
when S4 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
z_assignment:
z <= 0 when (seq_detect = S1 and x = 1) else
0 when (seq_detect = S1 and (x = 0 and not (x = 1))) else
0 when (seq_detect = S2 and x = 1) else
0 when (seq_detect = S2 and (x = 0 and not (x = 1))) else
0 when (seq_detect = S3 and x = 1) else
0 when (seq_detect = S3 and (x = 0 and not (x = 1))) else
1 when (seq_detect = S4 and x = 1) else
0 when (seq_detect = S4 and (x = 0 and not (x = 1))) else
0;
end sequence_detector_arch;
The testbench code for the sequence detector is,
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence_detector_tb is
end sequence_detector_tb;
architecture TB_ARCHITECTURE of sequence_detector_tb is
component sequence_detector
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end component;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal x : STD_LOGIC;
signal z : STD_LOGIC;
begin
UUT : sequence_detector
port map (
clk => clk,
rst => rst,
x => x,
z => z
);
clk_process : process
begin
clk <= 0;
wait for 5 ns;
clk <= 1;
wait for 5 ns;
end process;
sti_process: process
begin
x <= 0;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_sequence_detector of sequence_detector_tb is
for TB_ARCHITECTURE
for UUT : sequence_detector
use entity work.sequence_detector(sequence_detector_arch);
end for;
end for;
end TESTBENCH_FOR_sequence_detector;
Readers are recommended to read the following posts which are related to this blog post. A detailed steps to construct a sequential circuit is provided in the blog post- How to design Sequence Detector in 10 easy steps. Also another post useful in sequential circuit is- how to design Moore sequential circuit in Simulink. And futhermore this post- how to use Xilinx Schematic editor with example of sequence detector shows how xilinx software can be used to design and verify the sequence detector.
The state diagram of 1101 sequence detector is shown below-
State S1:
Beginning at state S1 when 0 is received it stays in the same state because it has nothing to remember and the output is 0 because the sequence 1101 is not detected. Only at the instant when 1101 sequence is detected the output is high, that is, 1. Also remember that the flip flops should be used when things are to be remembered by the circuit. When 1 arrives when in state S1, then it goes to next state S2 and it remembers that 1 was received which is part of the sequence 1101 which is to be detected.
State S2:
When in state S2, when 1 arrives, since it is part of the sequence it goes to next state S3, meaning it remembers 1. When 0 is received it cannot go to next state S3(since 1 received has occupied the transition condition and because 0 is not part of the sequence and there is nothing to remember), and it cannot remain in the same state S2 because this would mean 010 indefinite loop while in state S2, therefore it goes back to the initial state S1. Consider 100 is received and machine remains in S2 when 0 is received, then because of 1 the state changes from S1 to S2, then 0 is received then the machine stays in S2 and when another 0 is received then it stays again in S2. But consider when 100 is received and machine goes back to S1, then when 1 is received it changes state from S1 to S2, when 0 is received then goes back to S1 and when another 0 is received it stays in S1.
State S3:
When in state S3, when 0 is received then since it is part of the sequence 1101 it goes to new state S4 because the machine has to remember the new bit 0 as part of the sequence detection algorithm. When 1 is received it stays in the same state.
State S4:
When in state S4, when 1 is received then since it is part of the sequence 1101 to be detected it goes to S2. And when 0 is received then it goes back to initial state S1. At this point the machine outputs 1.
Following is a simulated digital waveform for the seqence 10101101010110001
The graph shows that the output z is high when 1101 is detected in the sequence x = 10101101010110001
The VHDL code for implementing this sequence detector is below-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity sequence_detector is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
x: in STD_LOGIC;
z: out STD_LOGIC);
end sequence_detector;
architecture sequence_detector_arch of sequence_detector is
type seq_detect_type is (
S1, S2, S3, S4
);
signal seq_detect: seq_detect_type;
begin
seq_detect_machine: process (clk)
begin
if clkevent and clk = 1 then
if rst=1 then
seq_detect <= S1;
else
case seq_detect is
when S1 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;
when S2 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S1;
end if;
when S3 =>
if x = 1 then
seq_detect <= S3;
elsif x = 0 then
seq_detect <= S4;
end if;
when S4 =>
if x = 1 then
seq_detect <= S2;
elsif x = 0 then
seq_detect <= S1;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
z_assignment:
z <= 0 when (seq_detect = S1 and x = 1) else
0 when (seq_detect = S1 and (x = 0 and not (x = 1))) else
0 when (seq_detect = S2 and x = 1) else
0 when (seq_detect = S2 and (x = 0 and not (x = 1))) else
0 when (seq_detect = S3 and x = 1) else
0 when (seq_detect = S3 and (x = 0 and not (x = 1))) else
1 when (seq_detect = S4 and x = 1) else
0 when (seq_detect = S4 and (x = 0 and not (x = 1))) else
0;
end sequence_detector_arch;
The testbench code for the sequence detector is,
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence_detector_tb is
end sequence_detector_tb;
architecture TB_ARCHITECTURE of sequence_detector_tb is
component sequence_detector
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end component;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal x : STD_LOGIC;
signal z : STD_LOGIC;
begin
UUT : sequence_detector
port map (
clk => clk,
rst => rst,
x => x,
z => z
);
clk_process : process
begin
clk <= 0;
wait for 5 ns;
clk <= 1;
wait for 5 ns;
end process;
sti_process: process
begin
x <= 0;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 1;
wait for 10 ns;
x <= 0;
wait for 10 ns;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_sequence_detector of sequence_detector_tb is
for TB_ARCHITECTURE
for UUT : sequence_detector
use entity work.sequence_detector(sequence_detector_arch);
end for;
end for;
end TESTBENCH_FOR_sequence_detector;
Embedded System Programming with C
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This is a beginner embedded system programming tutorial where it is shown how to write a C program that turns on a sound alarm when a switch is closed. The 80C51 microcontroller is used to do this. The switch is connected to the pin 0 of port 1 and the sound device is connected to the pin 0 of port 0. The C program continuously monitors the state of the switch and if the switch is switched On, then it sounds alarm that beeps 5 times with one second interval.
Following is the schematic diagram.
The C program is below:
#include <Reg51.H>
#define ON 0
#define OFF 1
sbit BUZZ = P0^0;
sbit BUTTON = P1^0;
void OneSec() // 1 sec delay function
{
unsigned int x;
for(x=0;x<33000;x++);
}
main() //main function
{
int i;
BUZZ = OFF;
while(1)
{
if(BUTTON==OFF)
{}
else
{
for(i=1;i<=5;i++)
{
BUZZ = ON;
OneSec();
BUZZ = OFF;
OneSec();
}
}
}
}
We defined ON and OFF as 0 and 1 using the preprocessor directive statements #define so that we can write ON and OFF keywords in the program code and it makes it easy to understand the code.
Then we defined two variables BUZZ and BUTTON as sbit data types and assigned them to the port 0, pin 0 and port 1, pin 0.
The OneSec() is a function which when executed takes 1 second. This function will be called in the main function to insert 1 second time interval between sound on and off.
The main function starts with variable initialization. The int i declares an integer i which will be required in outputting 5 signals to the sound device. Then BUZZ = OFF is used to make the port 0, pin 0 an output.
The while(1) statement is used to continuously execute the statements following it(read the state of switch and buzz sound). The if and else statements are used to sound the alarm if the switch is closed or not to sound if it is open.
In the above C program, we could have replaced while(1) with for(;;). Also we could have used while(BUTTON==OFF) instead of if(BUTTON==OFF) in which case the else(and the if) would not be required.
See another beginner embedded C programming tutorial- How to write C program to read/write ports of a microcontroller
How to transfer Eagle PCB design to Altium Designer
Cadsoft Eagle and Altium designer are widely used PCB design software. Altium designer users often find schematic, PCB and library in Cadsoft Eagle free file format and want to import them into Altium Designer. There is one trick that converts eagle design files to altium and that is using UCL scripts. But with newer Altium Designer version starting from v14 there is inbuild import program in Altium Designer software that converts Eagle files to Altium Designer.
Eagle provides many PCB designs and tutorials for free and in this post we are going to import one such design file to altium designer to see how the process of converting eagle to altium and also view imported file to see how they look like when they are converted.
Using the import feature is straight forward. The import function is under File > Import Wizard and this brings up the window like the one below,
Clicking Next, brings up the dialog box that allows us to specify what CAD files we want to import. Here we can see Eagle Projects and Designs listed in the list which was not previously on the list. We select that option.
After selecting that option and clicking next brings up the next window which allows us to add the Eagle schematic and PCB design files. The add button allows us to browse and select the eagle design files.
Then the next screen allows you to convert the eagle library files to altium designer library files. Since in this illustrated pcb design conversion there are no library it is left alone. But if you had eagle library files it good to convert them.
Then alitum designer reads the files for conversion.
The next window allows users to make various reports of the conversion process and specify what things to recognize such as power ports, any ports, net names and others as shown below-
The next screen allows user to specify directory where the converted design files should be saved. The default directory is the same directory as the input directory.
The conversion process starts which takes just seconds to complete. Then the conversion is completed where the user now just has to click on the Finish button.
The converted PCB file is shown below-
The schematic document and the PCB document are under the project file panel.
A glance of 3D view,
The converted schematic design is shown below.
As you can see the schematic and pcb files are very nicely and accurately transferred from Eagle to Altium Designer.
Cadsoft Eagle Free is widely used by students, electronics hobbyist and professional designers and Altium Designer is preferred for more professional PCB designs because of its features and 3D modelling capabilities. Both are very good PCB design software and both can be used for most of the electronics design work.
Eagle provides many PCB designs and tutorials for free and in this post we are going to import one such design file to altium designer to see how the process of converting eagle to altium and also view imported file to see how they look like when they are converted.
Using the import feature is straight forward. The import function is under File > Import Wizard and this brings up the window like the one below,
Clicking Next, brings up the dialog box that allows us to specify what CAD files we want to import. Here we can see Eagle Projects and Designs listed in the list which was not previously on the list. We select that option.
Then the next screen allows you to convert the eagle library files to altium designer library files. Since in this illustrated pcb design conversion there are no library it is left alone. But if you had eagle library files it good to convert them.
Then alitum designer reads the files for conversion.
The next window allows users to make various reports of the conversion process and specify what things to recognize such as power ports, any ports, net names and others as shown below-
The next screen allows user to specify directory where the converted design files should be saved. The default directory is the same directory as the input directory.
The conversion process starts which takes just seconds to complete. Then the conversion is completed where the user now just has to click on the Finish button.
The converted PCB file is shown below-
The schematic document and the PCB document are under the project file panel.
A glance of 3D view,
The converted schematic design is shown below.
As you can see the schematic and pcb files are very nicely and accurately transferred from Eagle to Altium Designer.
Cadsoft Eagle Free is widely used by students, electronics hobbyist and professional designers and Altium Designer is preferred for more professional PCB designs because of its features and 3D modelling capabilities. Both are very good PCB design software and both can be used for most of the electronics design work.
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